1. Field of the Invention
The present invention relates to semiconductor fabrications, and particularly, relates to a method for fabricating a dielectric layer with improved insulating properties and a method for fabricating a semiconductor structure having a dielectric layer with improved insulating properties.
2. Description of the Related Art
In semiconductor fabrication, various layers of dielectric insulating materials, semiconductor materials and conducting materials are formed to produce a multi-level semiconductor device.
One of the limiting factors of the continued evolution toward smaller device sizes and higher densities of semiconductor devices has been insufficient insulation properties of dielectric insulating materials formed in the semiconductor device for isolating metal interconnects and passive or active components therein, since thickness or space of the dielectric insulating materials is also reduced.
For example, silicon oxide is one of the widely used dielectric insulating materials which function as an insulating layer in applications such as multilevel interconnections, shallow trench isolations (STI), gate spacers, and source or drain contact isolations. A silicon oxide film can be deposited by a thermal chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) process. However, after a front-end process of the semiconductor device is completed, a sequentially formed silicon oxide film will be formed under a relatively low temperature (e.g. a temperature not greater than 600° C.) to prevent the devices (e.g. CMOS devices) formed in the front-end process from degrading. This relatively low temperature, however, may degrade insulating properties such as bulk resistivity, leakage current, electrical breakdown voltage and mechanical and chemical stability of the formed silicon oxide while the thickness thereof is further reduced.
Thus, there is a need for a method to fabricate a dielectric layer with improved insulating properties, which allows the thickness of the insulating layer to shrink along with other features such as a metal interconnect line width or a space between adjacent passive/active devices or metal interconnect lines.